A clock and data are superposed on a digital signal transmitted from a transmitter to a receiver and the clock and the data need to be recovered at the side of the receiver. A clock data recovering (CDR) apparatus to perform the recovery is described in J. Terada, et al. “A 10.3125 Gb/s Burst-Mode CDR Circuit using a ΔΣDAC,” ISSCC Dig. Tech. Papers, pp. 226-227 (2008) (Non-Patent Document 1), for example.
The clock data recovering apparatus described in Non-Patent Document 1 detects an edge of an input signal, recovers a clock on the basis of timing of the edge, and recovers data of the input signal at each timing indicated by the clock. A clock generating apparatus that is included in the clock data recovering apparatus and generates a recovered clock includes a phase lock loop (PLL) that is configured to include a gated voltage controlled oscillator (GVCO), a divider, a phase difference detector, an up-down counter, and a DA converter of a ΔΣ system.
The clock data recovering apparatus described in Non-Patent Document 1 is an apparatus that operates in a burst mode. That is, the clock generating apparatus receives a reference clock from the outside before a signal input starts or during the signal input and outputs a clock of the same frequency as a frequency of the reference clock. If the signal input starts, the clock generating apparatus matches a phase of the clock with a phase of an input signal in short time and outputs the clock.
In addition, a clock data recovering apparatus described in Japanese Patent Application Laid-Open No. 2014-60520 (Patent Document 1) is an apparatus that operates in a burst mode. If a signal input starts, the clock data recovering apparatus can match a phase of a clock with a phase of an input signal in short time and can output the clock. The clock data recovering apparatus does not need to receive a reference clock from the outside and can reduce a circuit scale.